In modern semiconductor manufacturing, large memory arrays are often fabricated by combining a number of smaller memory sections in an effort to economically make the larger array. The bitlines in a particular column of a memory array often require precharging prior to reading and/or writing to the particular cells. Precharging is generally required for memory cells to prevent data disturb issues due to charge sharing. As memory depths increase, the depth of each of the memory sections within the larger memory array also increases. Specifically, the number of cells in a particular column of modern memory devices has become quite large. If each of the smaller sections of a memory array are precharged simultaneously, which was often done in conventional approaches, an excessive amount of current may be drawn. The excessive amount of current is generally undesirable in an integrated circuit seeking to have a low overall heat generation, a high mean time between failures (MTBF), a low noise on power busses, etc.
Referring to FIG. 1, a conventional memory array 10 is shown. The memory array 10 generally comprises a write multiplexor 12, a read multiplexor 14, a memory array 16, a read pointer control block 18 and a write pointer control block 20. The memory array 16 generally comprises a number of bitlines 22a-22n. If a number of the bitlines 22a-22n are charged high at the same time, the precharging may draw an excessive amount of current, particularly in a dense memory array 10.
One way to limit the peak current used when precharging a bitline includes using a current limiting circuit. Additionally, differential sense amplifiers (which require a precharge but don't draw much current) may be implemented that do not discharge the bitlines all the way to the ground or VSS potential. While such a technique may limit the amount of precharge current necessary, it may suffer from the drawbacks of generally requiring more chip area to implement and is generally simulation intensive. A current limiting technique may require both hot and cold testing since the usage of a reference voltage used in the current limiting circuit may vary under such conditions. The requirement for both hot and cold testing generally increases the cost of back-end testing and may slow production.